A Hardware-Software Co-Design Framework for Energy Efficient LSTM Based SoC Estimation on Resource-Constrained FPGAs

Sagar Vijay Mhatre; Vinitkumar Jayaprakash Dongre; Sudhakar Mande

doi:10.57159/jcmm.5.3.26806

Authors

Sagar Vijay Mhatre Department of Electronics and Telecommunication, K J Somaiya Institute of Technology, Mumbai, India
Vinitkumar Jayaprakash Dongre Department of Electronics and Telecommunication, Thakur College of Engineering, Mumbai, India
Sudhakar Mande Department of Electronics and Telecommunication, Don Bosco Institute of Technology, Mumbai, India

DOI:

https://doi.org/10.57159/jcmm.5.3.26806

Keywords:

State-Of-Charge (SoC) Estimation, LSTM Neural Networks, FPGA Acceleration, Hardware-Software Co-Design

Abstract

The rapid proliferation of electric vehicles drives the need for accurate, real-time and energy-efficient Battery Management Systems. The conventional model-based approach can't address the need due to complex and non-linear battery operations. LSTM based network provide better accuracy due to their inherent capability to capture temporal dependencies. However, this makes its deployment on the low-cost edge hardware challenging due to stringent constraints on power, latency and on-chip resources. To address the issue, a three-stage software-hardware codesign methodology is proposed. It includes Python-based software evaluation and parameter selection, hardware estimation using High Level Synthesis and physical deployment on an FPGA platform. Pareto analysis is used to identify the optimal configurations that balance the accuracy with the hardware requirements, such as inference latency and resource utilization, to achieve efficient deployment. Design Space Exploration (DSE) is performed to evaluate the different configurations with different model architectures, temporal window size and quantization policies. A State of Charge inference engine for the NASA Lithium-Ion Battery dataset is deployed on a resource-constrained Pynq Z2 board using the proposed codesign framework. It demonstrates strong consistency between the software and hardware domains, with the Pearson coefficient exceeding 0.90. The average accuracy transfer with only 0.834% degradation. Additionally, it is also shown that uniform 8-bit fixed-point quantization preserves accuracy while significantly improving the hardware deployment. This suggests that a uniform quantization policy works well for small neural network architectures. The experiment demonstrates better per-dollar energy efficiency (GOPS/W/$) than many state-of-the-art implementations. Overall, this work provides a structured and validated approach for jointly optimizing algorithm and hardware parameters. This enables efficient deployment of deep learning models on the resource-constrained hardware platforms.

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